Clock and data recovery (CDR) is widely used in digital communication. Most monolithic CDR implementations use a phase locked loop (PLL), which typically includes a phase detector (PD), a charge pump (CP), some type of loop filter and a voltage controlled oscillator (VCO). Many CDRs also need a frequency acquisition mechanism to assist the phase locking, which requires an external reference clock source, like a crystal oscillator.
Bang-bang CDR architectures use a bang-bang VCO, which has a bang-bang digital input directly connected to a phase and/or frequency detector. The digital bang-bang input can change the VCO frequency instantaneously by a small amount, which is called a bang-bang frequency, fbb. This type of architecture can stabilize the PLL, make the loop filter much easier to design, and allowing the CDR jitter transfer and jitter tolerance corner frequency to be much easier to control. Typical bang-bang VCOs, however, are ring-based oscillators. As data rates move higher and higher, especially greater than 10 gigabytes per second (Gb/s), an inductor-capacitor (LC) tank-based VCO has advantages over a ring-based VCO, such as lower phase noise, making it easier to operate at high frequencies.